In many applications, it is desirable to switch between two clock signals. An example of such an application is in the area of switch mode power supplies. Typically, a switch mode power supply requires a clock signal be coupled to a control unit for generating a pulse width modulated signal. The clock signal is typically generated internally in the power supply. However, it is also desirable for the power supply to have the ability to use an externally supplied clock signal so that the operation of a plurality of switch mode power supplies can be synchronized. Thus, there is a need to design a circuit which normally couples the internally generated clock signal to the control unit, but which can couple an externally supplied clock signal to the control unit whenever the external clock signal is coupled to the power supply.
A common prior art device for switching between two input clock signals is a simple switch, wherein each of the two input clock signals is coupled to the device through a respective switch input terminal and wherein a selected one of said clock signals is coupled to an output terminal as a function of the present state of the switch. One disadvantage of this method is that external intervention is required to control the state of the switch, e.g., the switch needs to be manually toggled by the user. Another disadvantage is that the changeover is not smooth, such that the output clock could be held at a logic "low" or logic "high" state for an excessive period of time. For some circuit users of the device's output, such an output clock signal held for an excessive period of time in one logic state could be detrimental. In some switching power supplies, for example, the holding of the clock signal in one state for too long could cause the switching transformer to saturate and short-circuit, especially during the initial power-up.
Where the switch is electronically controlled, an additional terminal is also required for receipt of an externally generated control signal. The externally generated control signal provides the timing for the switch transitions for selecting between one input clock signal and the other. One disadvantage of this prior art device is that, in some applications, it may not be possible to add an additional terminal to a system because the number of input/output (I/O) terminals in the system are limited by packaging constraints. Another disadvantage of this prior art device is that the state of the control signal needs to be synchronized with the clock signals to ensure that an appropriate clock signal is provided at the output of the device for use by a subsequent circuit. If one of the clock signals is not functioning or is not connected to its input terminal, a clock signal will not appear at the device output when the control signal is set to select the non-functioning clock signal. For some circuit applications, the absence of a clock signal can be detrimental. In some switching power supplies, for example, the absence of the clock signal could cause the switching transformer to saturate and short-circuit under certain circumstances.
The present invention is directed towards overcoming the above mentioned disadvantages and drawbacks of the prior art, i.e., the need for an additional control terminal and the requirement that the control signal and the external clock signals be synchronized. An advantage of the present invention is that it provides a clock changeover device of improved performance and reliability as compared with prior clock changeover devices.